The case for Labeled von Neumann Architecture

(LvNA)

Sunday, June 3, 2018 
8:20 AM - 12:00 PM 
Los Angeles, California

 

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Abstract


Conventional instruction set architecture (ISA) defines the functional abstraction between software and hardware. Contemporary hardware design focuses on two goals. One is to implement ISA correctly to support the running of applications. Another is to optimize datapath to make applications run faster.

However, uncertainty becomes a new problem after the emergence of multi-core architecture. One example is that, uncertainty reduces applications' quality of services (QoS) in data centers. Therefore, contemporary data centers are confronting with challenges in managing the trade-offs between resource utilization and applications' QoS. Another example is that, multi-core is usually disabled in aviation areas to avoid uncertainty. To make better use of the wasted computing resources, uncertainty is the critical problem to address.

To actually reduce uncertainty, as suggested in the community white paper “21st Century Computer Architecture”, computer architecture needs to provide new, higher-level interfaces beyond a conventional ISA to convey an application's semantics to the hardware. After that, hardware can leverage such semantics to manage share resources in a more predictable way.

In this tutorial, we will present these challenges first. And then we will introduce a novel architecture, Labeled von Neumann Architecture (LvNA), to convey the software semantics down to hardware. The main idea of LvNA is to enforce distinguishability, isolation and prioritization (DIP properties) to hardware by labels. Based on the concept of LvNA, we design policies for different kinds of resources. Moreover, we will show that the principle of LvNA can also be applied to managing storage resources in terms of Flash-based Solid State Drives (SSD). To verify these ideas, we will also demonstrate our FPGA prototype, Labeled RISC-V, and apply the software-hardware co-design polices on it to present the evaluation.

Labeled RISC-V has been already open-sourced at https://github.com/LvNA-system/labeled-RISC-V.

 

Topics


This tutorial will cover the following topics.

  1. overview of the challenges about uncertainty
  2. DIP properties and LvNA
  3. design and implementation of Labeled RISC-V
  4. FPGA prototype demo of Labeled RISC-V
  5. design and implementation of labeled storage container based on Open SSD

 

Audience


Target Audience: researchers interested in enforcing distinguishability, isolation and prioritization to hardware (for example, datacenter, real-time systems, and solid state drives), researchers interested in RISC-V

Pre-requisite Knowledge: architecture/microarchitecture design

 

Schedule


08:20 AM - 09:00 AM

Talk: The case for Labeled von Neumann Architecture

09:00 AM - 09:10 AM

10 Minute Break

09:10 AM - 10:00 AM

 

Demo: Enforcing DIP properties with Labeled RISC-V

* sub-demo 1: distinguishability - label-based performance counters
* sub-demo 2: isolation - virtualization without software hypervisors
* sub-demo 3: prioritization - label-based cache partition and memory bandwidth management

 

10:00 AM - 10:10 AM

10 Minute Break

10:10 AM - 10:50 AM

Talk: Labeled RISC-V internals

10:50 AM - 11:00 AM

10 Minute Break

11:00 AM - 11:30 AM

Talk: Labeled Storage Container based on Open SSD

11:30 AM - 12:00 PM

Discussion

 

Presenters


Yungang Bao is a professor of the State Key Laboratory of Computer Architecture, Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He is the executive director of Research Center for Advanced Computer System (ACS) . He received his BS degree in computer science from Nanjing University in 2003, and his PhD degree in computer engineering from ICT, CAS in 2008, supervised by Prof. Jianping Fan and Prof. Mingyu Chen. During his PhD study, he led the Hybrid Hardware/Software Memory Trace Tool (HMTT) project. During 2010-2012, he did postdoc research in Department of Computer Science, Princeton University, working with Prof. Kai Li on the Princeton Application Repository for Shared-Memory Computers (PARSEC) project. He was the winner of CCF-Intel Young Faculty Researcher Program of the year for 2013. 

 

 

 

 

Sa Wang is an assistant professor of the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include operating systems, distributed systems, cloud computing and now with a focus on software defined cloud computing.

 

 

 

 

 

Zihao Yu is a PhD candidate of the Institute of Computing Technology, Chinese Academy of Sciences. He is supervised by Prof. Ninghui Sun and Prof. Yungang Bao. He received his B.S. degree in computer science from Nanjing University in 2014. His research interests include computer architecture and operating systems. He is the leader of the Labeled von Neumann Architecture (LvNA) project.

 

 

 

 

 

Dejun Jiang is an associate professor at the Institute of Computing Technology, Chinese Academy of Sciences. He has received the B.E. degree from Beihang University, the M.E. degree from Tsinghua University, and the Ph.D. degree from Vrije Universiteit Amsterdam, Netherlands. His research interests span storage systems, memory architecture, operating systems, and distributed systems, and now with a focus on building systems for emerging non-volatile memories and applications. Dr. Jiang has published papers in ATC, PACT, ICS, ICCD, WWW and so on. His research work has been widely cited. He has served as PC member/reviewer in Transactions and Conference peer reviewings such as TOS, TACO, CCGrid, ICS, Computer Frontier.

 

 

 

 

 

 

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