Conventional instruction set architecture (ISA) defines the functional abstraction between software and hardware. Contemporary hardware design focuses on two goals. One is to implement ISA correctly to support the running of applications. Another is to optimize datapath to make applications run faster.
However, uncertainty becomes a new problem after the emergence of multi-core architecture. One example is that, uncertainty reduces applications' quality of services (QoS) in data centers. Therefore, contemporary data centers are confronting with challenges in managing the trade-offs between resource utilization and applications' QoS. Another example is that, multi-core is usually disabled in aviation areas to avoid uncertainty. To make better use of the wasted computing resources, uncertainty is the critical problem to address.
To actually reduce uncertainty, as suggested in the community white paper “21st Century Computer Architecture”, computer architecture needs to provide new, higher-level interfaces beyond a conventional ISA to convey an application's semantics to the hardware. After that, hardware can leverage such semantics to manage share resources in a more predictable way.
In this tutorial, we will present these challenges first. And then we will introduce a novel architecture, Labeled von Neumann Architecture (LvNA), to convey the software semantics down to hardware. The main idea of LvNA is to enforce distinguishability, isolation and prioritization (DIP properties) to hardware by labels. Based on the concept of LvNA, we design policies for different kinds of resources. To verify these ideas, we will also demonstrate our FPGA prototype, Labeled RISC-V, and apply the software-hardware co-design polices on it to present the evaluation.
Labeled RISC-V has been already open-sourced at https://github.com/LvNA-system/labeled-RISC-V.
This tutorial will cover the following topics.
- overview of the challenges about uncertainty
- DIP properties and LvNA
- design and implementation of Labeled RISC-V
- FPGA prototype demo of Labeled RISC-V
Target Audience: researchers interested in enforcing distinguishability, isolation and prioritization to hardware (for example, datacenter, real-time systems), researchers interested in RISC-V
Pre-requisite Knowledge: architecture/microarchitecture design
Talk: Labeled RISC-V: A Case for Software-Defined Architecture [PDF]
- Background - Utilization vs. User experience
- Challenge - Weak Control
- Solution - Labeled architecture model
- [Video Demo & Break]
- Design - PARD
- Implementation & Live Demo - Labeled RISC-V
- Future works
- Conclusion & Discussion
- ARM Research Summit keynote slide
- ARM Research Summit keynote video
Yungang Bao is a professor of the State Key Laboratory of Computer Architecture, Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He is the executive director of Research Center for Advanced Computer System (ACS) . He received his BS degree in computer science from Nanjing University in 2003, and his PhD degree in computer engineering from ICT, CAS in 2008, supervised by Prof. Jianping Fan and Prof. Mingyu Chen. During his PhD study, he led the Hybrid Hardware/Software Memory Trace Tool (HMTT) project. During 2010-2012, he did postdoc research in Department of Computer Science, Princeton University, working with Prof. Kai Li on the Princeton Application Repository for Shared-Memory Computers (PARSEC) project. He was the winner of CCF-Intel Young Faculty Researcher Program of the year for 2013.
Zihao Yu is a PhD candidate of the Institute of Computing Technology, Chinese Academy of Sciences. He is supervised by Prof. Ninghui Sun and Prof. Yungang Bao. He received his B.S. degree in computer science from Nanjing University in 2014. His research interests include computer architecture and operating systems. He is the leader of the Labeled RISC-V project.
Huizhe Wang is a Master candidate of the Institute of Computing Technology, Chinese Academy of Sciences. He is supervised by Prof. Yungang Bao. He received his B.S. degree in computer science from Nanjing University in 2017. His research interests include computer architecture and compiling techniques. He participates in the Labeled RISC-V project.
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